This invention relates to an ultra large scale integrated (ULSI) circuit of low internal operating voltage which has a memory capacity of, for example, 16M bits or more and more particularly to improvements in the construction and characteristics of a voltage limiter circuit and a reference voltage generator which are used in the above type of ULSI circuit, methods of testing the ULSI circuit incorporating the voltage limiter circuit and reference voltage generator, and the layout of actual ULSI circuits.
This invention is particularly concerned with a reference voltage generator of semiconductor device capable of generating stable voltage which changes less under the influence of external power supply voltage and temperatures.
Occasionally, the semiconductor integrated circuit needs a stable reference voltage which change less with external power supply voltage and temperatures. This may be mentioned in connection with voltage limiters of LSI circuits as described in, for example, ISSCC Digest of Technical Papers, pp. 282-283, February 1984, ISSCC Digest of Technical Papers, pp. 270-271, February 1986 and ISSCC Digest of Technical Papers, pp. 272-273, February 1986. Particularly, the last paper describes that in a memory LSI circuit such as DRAM (Dynamic Random Access Memory), a voltage lower than external power supply voltage is generated by means of a circuit (voltage limiter) formed on an LSI chip and is used as power supply for the memory LSI circuit. Such an internal power supply voltage must be a stable voltage which changes less under the influence of the external power supply voltage and temperature for making memory operation stable and to this end, a stable reference voltage is required. Further, an LSI circuit having a built-in analog circuit often requires stable reference voltages used as voltages for reference comparison.
A reference voltage generator complying with the above requirements has been proposed as disclosed in, for example, U.S. Pat. Nos. 3,975,648 or 4,100,437. FIG. 1A of the present application illustrates the proposed circuit. Specifically, this circuit utilizes the difference in threshold voltage between an N-channel enhancement type MOSFET (hereinafter simply referred to as EMOS) and an N-channel depletion type MOSFET (hereinafter simply referred to as DMOS) to produce a stable voltage. In FIG. 1A, Q.sub.91 designates an EMOS, Q.sub.90, Q.sub.92 and Q.sub.93 designate DMOS'S, V.sub.CC designates an external power supply of positive voltage and V.sub.BB designates an external power supply of a negative voltage. The difference between a threshold voltage of EMOS and that of DMOS equals an output voltage V.sub.R as will be seen from the following operational description of this circuit.
Given that current flowing through Q.sub.90 and Q.sub.91 is I.sub.90 and current flowing through Q.sub.92 and Q.sub.93 is I.sub.91, the following four equations stand when all of the four MOSFET's operate in their saturation regions: ##EQU1## where V.sub.99 is voltage at a node 99, V.sub.TE is threshold voltage of the EMOS where V.sub.TE &gt;0, V.sub.TD is threshold voltage of the DMOS where V.sub.TD &lt;0, and .beta..sub.90, .beta..sub.91, .beta..sub.92 and .beta..sub.93 are conductance coefficients of Q.sub.90, Q.sub.91, Q.sub.92 and Q.sub.93, respectively. From equations (1) to (4), there results ##EQU2## If device parameters of each MOSFET are determined such that .beta..sub.90 and .beta..sub.93 are sufficiently small or .beta..sub.90 /.beta..sub.91 =.beta..sub.93 /.beta..sub.92 is EQU satisfied, V.sub.R =V.sub.TE -V.sub.TD ( 6)
is obtained, indicating that a voltage equal to the difference in threshold voltage between the EMOS and DMOS is produced as output voltage V.sub.R and that this voltage does not depend on the external power supply voltages V.sub.CC and V.sub.BB.
In recent years, high integration of semiconductor devices has made progress and concomitant scale-down of the semiconductor devices has raised a problem that their breakdown voltage is degraded. This problem can be solved by decreasing power supply voltage applied to the semiconductor device. However, this measure is not always preferred when the external interface is taken into consideration. Under the circumstances, a method has been proposed wherein while the level of power supply voltage externally applied remains unchanged as compared to the prior art (for example, 5 V for TTL (Transistor Transistor Logic) compatible type), all internal power supply of a lower voltage than that level (for example, 3 V) is formed in a semiconductor device. For example, IEEE Journal of Solid-State Circuits, Vol. SC-22, No. 3, pp. 437-441, June 1987 describes an instance where this method is applied to a DRAM and a circuit (voltage limiter circuit) for generating an internal power supply from an external power supply.
FIG. 1B is a circuit diagram of the voltage limiter circuit described in the above literature. As shown, a voltage limiter circuit VL comprises a reference voltage generator VR and a driver B. Connected to the voltage limiter circuit VL is a load Z or a circuit which operates using output voltage V.sub.L of the voltage limiter as power supply. The reference voltage generator VR provides a stable voltage V.sub.R which changes less under the influence of external power supply voltage V.sub.CC and temperatures. The driver B generates a voltage V.sub.L which is of the same level as that of V.sub.R and which has great drivability, and it comprises a differential amplifier DA including transistors Q.sub.106 to Q.sub.111 and an output MOS transistor Q.sub.112. The differential amplifier DA has two input terminals of which one is connected to V.sub.R, with the output voltage V.sub.L being fed back to the other input terminal and this circuit operates to permit the output voltage V.sub.L to follow the input voltage V.sub.R. The drivability of the output voltage V.sub.L is determined depending on the channel width of the output MOS transistor Q.sub.112. Accordingly, by designing the transistor Q.sub.112 such that it has a channel width commensurate with current consumption, stable internal power supply voltage V.sub.L can be supplied to the load.